Fabric Reset Enable - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

Fabric Resets can be enabled from PS - PL Configuration > General > Fabric Reset Enable or by setting PSU_NUM_FABRIC_RESETS properly. Up to four PL Reset signals (pl_resetn{0:3}) can be enabled with the default being one reset signal enabled. PL Fabric Resets are Asynchronous to PS to PL clock (pl_clk{0..3}).

There are a total of four PS-PL resets that are available. These four PL resets that are user selectable from within the PCW use the available last four out of the 96 EMIOs. Based on their selection from 0-4, the number of EMIO is reduced from 96 to 92 which should be taken into account. The selection for the fabric reset can be done from the General node available in the PS-PL configuration page.

The corresponding registers required to toggle the EMIOs for realizing the PL resets is taken care of by the PCW through output files that are generated as a part of output products.