DDR Software Self-Refresh - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

DDR Software Self Refresh is a TCL-only parameter (not displayed in the wizard User Interface).

The default value for this parameter ( PSU__DDR_SW_REFRESH_ENABLED ) is enabled and must not be disabled. The presence and state of this parameter reserves the lower DDR (0x7ff00000 to 0x7fffffff when lower 2GB DDR is enabled) for Xilinx's use only (This memory is used for APU restart and it is always required to be enabled for the PMU by default). Please ensure that this reserved area is not accessed by your application.