DDR Memory Options - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

Speed Bin – Device speed grade. The speed bin should be set to the actual frequency for best performance. Letters defined by the JEDEC specification.

CAS Latency (cycles) Column Access strobe latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module. When using DBI, do not increase the latency by 2 cycles, as this is handled by the controller when the DBI is enabled.

CAS Write Latency (cycles) Write latency setting in memory clock cycles.

Additive Latency (cycles) Additive latency setting in memory clock cycles.

RAS To CAS (cycles) Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS).

Precharge Time (cycles) Precharge time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row

tRC (ns) Row cycle time

tRASmin (ns) Minimum number of memory clock cycles required between an Active and Precharge command.

tFAW (ns) Determines the number of activates that can be performed within a certain window of time.

DRAM IC Bus Width (per die) Width of individual DRAM components

DRAM Device Capacity (per die) Storage capacity of individual DRAM components

Bank Group Address Count (Bits) Number of bank address pins

Bank Address Count (Bits) Number of Bank address pins

Row Address Count (Bits) Number of Row address pins

Col Address Count (Bits) Number of Column address pins

DDR Size (in Hex) Total DDR Size

Dual Rank - Enables the second rank/CS_N pin

Note: Hover on each of the above memory options in IP User Interface to find additional information.