Customizing and Generating the Core - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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This section includes information about using the Vivado Design Suite to customize and generate the core.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 3] for detailed information. The IP integrator might auto-compute certain configuration values when validating or generating the design, as noted in this section. To check whether the values do change, see the description of the parameters in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core in the IP integrator using the following steps:

1. Select the IP from the Vivado IP catalog.

2. Double-click the selected IP, or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 4] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 5] .

The Zynq UltraScale+ Block Design page with a block diagram appears in the window ( This Figure ). Review the contents of the block diagram. The green colored blocks in the diagram are configurable.

TIP: To open the corresponding configuration page, you can click a green block, or select the page in the Page Navigator at the left side.

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). This layout might vary from the current version.