Clocking Options - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

Memory Interface Device Frequency (MHz) This is the requested frequency for the DDR memory part. This Interface is the actual frequency from the PLL which drives the DDR. All the DRCs for the timing parameter are computed based on the actual interface frequency.

DDR Controller Options

Memory Type – Type of memory interface. For more details about different memory types, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .

Components Types of the components supported by the memory controller.

Effective DRAM Bus Width Data width for DDR interface, not including ECC data width

ECC Enables Error correction code support.