CSU and Tamper Response Settings - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

CSU is responsible for loading the processing system (PS) first-stage boot loader (FSBL) code into the on-chip RAM (OCM) in both secure and non-secure boot modes. You can select, through the boot header, to execute the FSBL on the Cortex®-R5 or the Cortex-A53 processor. After FSBL execution starts, the CSU enters the post-configuration stage, which is responsible for system tamper response.

The CSU can be configured to have secure lock down, system reset, and system interrupt for some of the errors like PL single event upset (SEU) error, Temperature alarm, voltage alarm, etc. These options are available under CSU Tamper Response settings on the Advanced Configuration page.