AXI4 I/O Compliant Interfaces - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

Following are the AMBA® AXI4 compliant interfaces:

Three PS General Purpose Master interfaces user configurable as 32, 64, and 128 bits in width. The default width is 128.

Seven PL General Purpose Master interfaces user configurable as 32, 64, and 128 bits in width. The default width is 128.

A 128-bit PL Master AXI coherency extension (ACE) interface for coherent I/O to A53 L1 and L2 cache systems

A 128-bit PL Master ACP interface to support L2 cache allocation from PL masters.
Limited to 64-byte cache line transfers only

See PS-PL Configuration .