Programmable Logic Interrupts - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
Release Date
3.3 English

The Control Interfaces and Processing System IP core provides three PS to PL interrupt interfaces (in turn these has wide number of shared interrupts for each peripheral) and 16 PL to PS interrupts. Also, the CIPS IP core has a list of Processor and Debug interrupts.

The Interrupt Configuration tab is used to enable/disable the interrupts between the CIPS core and the PL.

These are broadly categorized as the following:
PS to PL
We have wide number of shared interrupts from different regions of PS (LPD, FPD,and PMC) to PL masters or slaves. You can enable these interrupts separately for each domain and can connect each peripheral interrupt signal to PL logic.
PL to PS
There are 16 PL to PS interrupts that are supported. These are shared interrupts from PL logic to GICs of Real-time Processing Unit (RPU) and Application Processing Unit (APU).
High priority PL to PS cores (Processor)
These are Legacy FIQ/IRQ interrupts for RPU/APU from PL. One IRQ and FIQ per CPU will be routed from PL to GIC.
Inter Processor Interrupt
The Inter Processor Interrupt Block provides the ability for any processing unit to interrupt another processing unit by performing a register write. There are seven IPI channels (IPI 0 through IPI 6), which can be assigned to APU, RPU, and PL.
Figure 1. Interrupt Configuration

The interrupts from the Control, Interfaces and Processing System IP core I/O peripherals (IOP) are routed to the PL. The PL can asynchronously assert up to 20 interrupts to the PS cores like APU/RPU.

  • 16 interrupt signals are mapped to the interrupt controller as a peripheral interrupt where each interrupt signal is set to a priority level and mapped to one or both CPUs. To use more than one interrupt signal, use a Concat block in the Vivado IP integrator to automatically size the width of the interrupt vector.
  • The remaining four PL interrupt signals are inverted and routed to the nFIQ and nIRQ interrupt directly to the signals to the private peripheral interrupt (PPI) unit of the interrupt controller. There is an nFIQ and nIRQ interrupt for each of two CPUs.

The Interrupt IDs are exported to SW and the same ID can be seen in xparameters.h file or see the Versal Adaptive SoC Technical Reference Manual (AM011).