PMC Power Domain Clocks - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English
Processor/Memory Clocks
Clock configuration for the HSM0, which is source for AIE PLL. HSM1 which is source for DDR PLL. HSM0 and HSM1 connectivity is dedicated and not shown in the IP integrator canvas.
Peripherals/IO Clocks
Clock configuration for boot devices like OSPI, SD/eMMC, and clocks for NPI and NoC.
Interconnect and Switch Clocks
Clock configuration for interconnects and switches in PMC domain.