PLL Options for Output Clocks - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

There are four PLLs available in the AMD Versal™ PS and PMC that are spread across the 3 domains, PMC, LPD and FPD. There are two PLLs namely PPLL and NPLL in the PMC domain while the RPLL in the LPD domain and APLL in FPD domain. The Control, Interfaces and Processing System IP core provides an option to make use of the cross domain PLLs to be used to source the cross-over peripheral. This gives additional options to select from a pool of all PLLs.

Table 1. PLL Options
PLL Option Description
Name One of the four PLLs available in APLL, RPLL, PPLL, and NPLL.
Source This is the source PLL for the corresponding peripheral.
Multiplier (FBDIV) Denotes the 6-bit Integer value which will be used as multiplier in calculating the respective PLL output frequency.
CLKOUTDIV Enable the divide by 2/4/8 function inside the PLL. The output of this will be the actual output frequency of respective PLL.
PLL output (MHz) Final output frequency of the respective PLL.
Cross domain Paths Denotes the cross-domain name as APLL_TO_LPD for FPD PLLs, NPLL/PPLL_TO_FPD for PMC PLL’s and RPLL_TO_FPD for LPD PLLs.
Divisors Denotes the 6-bit integer value. This value will be used as divisor in calculating the cross-domain output frequency for respective PLL.
Output frequency (MHz) PLL output frequency for cross domain.

In the Auto mode, you may not get the actual frequency that is requested due to the load of different clocks on the same source PLL. After instantiating the CIPS IP core, some clocks are enabled by default as per the clocking sheet of the respective part.