PL Clocks - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

The Versal device Control, Interfaces and Processing System provides four clocks to the PL. Versal CIPS IP core enables the configuration of these clocks to be used in the PL. The Versal CIPS core inserts a BUFG for each of the PL clocks. Also, PCW provides option to select IRO clock to enable and connect to PL peripherals.

It is also possible to disable BUFG_PS insertion in the CIPS IP, allowing you to instantiate a different compatible clock buffer. To do so, the following Tcl command should be used inside IP Integrator:
set_property -dict [list CONFIG.PS_PMC_CONFIG \{PS_PMCPL_CLK0_BUF 0 PS_PMCPL_CLK1_BUF 0 PS_PMCPL_CLK2_BUF 0 PS_PMCPL_CLK0_BUF 0 PS_PMCPL_IRO_CLK_BUF 0 } ] [get_bd_cells versal_cips_0]

You can use PMC domain PLLs in FPD and LPD but the reverse is not allowed because only forward path clocking is followed in CIPS.

Table 1. Output Clocks and their Descriptions
Output Clock Description
Source This is the source PLL for the corresponding peripheral.
Requested Freq (MHz) This is the input frequency given to the corresponding peripheral.
Divisor 0 Denotes the 6-bit programmable divisor.
Actual Freq (MHz) This is the actual frequency calculated by the processor configuration. The clocking algorithm works with multiple factors, peripherals, PLLs, and priorities. Therefore, in certain cases, the actual frequency might be different than the requested frequency.
Range (MHz) This is the minimum/maximum range of the frequency that the corresponding peripheral can work with. In this mode, you must configure the M and D values to achieve the desired frequency. When this mode is enabled, the values requested through the output mode are overwritten.
Note: In order to modify the clock frequencies/divisors, the corresponding clock must be enabled.