Output Clocks - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

This section displays the default/user selected peripheral clocks that are allowed to update the frequency. Also, output clocks hold different domain PLLs.

PLLs in the PS and PMC are:

APLL
APU PLL is in the FPD domain.
NPLL
NoC PLL is in the PMC domain.
RPLL
RPU PLL is in the LPD domain.
PPLL
PMC PLL is in the PMC domain.

In the default mode (when the manual mode is turned off), the core automatically chooses the source PLLs and calculates the M (Multiplier) and D (Divisor) values to ensure that the tool meets the requested frequency to the nearest possible value. The core might not achieve all the requested values, because each PLL caters to multiple peripherals. An internal algorithm creates the best possible solution based on the following conditions.

The algorithm chooses source PLL on its own and the rule is that the PMC domain PPLL, NPLL can be used to source in the LPD and FPD. The LPD domain RPU PLL can be used to source in the FPD, vice-versa is possible only by setting cross domain PLL parameter.

  • When ethernet is enabled, the core tries to give precedence to the solution which has the ethernet frequency of 125 MHz. In the manual mode, divisors should be made to obtain either of 125/25/2.5 MHz.
  • When ethernet is enabled and if there are multiple clocking solutions with the identical ethernet frequency of 125 MHz, then the tool takes precedence of the solution that has the least possible total error (sum of requested frequencies-sum of actual frequencies) value of various peripherals.
  • The LPD_TOP_SWITCH_CLK frequency must always be at least 1.5x faster than the LPD_LSBUS_CLK.
  • The NoC clock should always be higher than the NPI clock frequency.
  • The tool takes precedence of the solution with least possible total error value of various peripherals even when the ethernet is disabled.
  • The tool generates CAN clocks within 0.25% tolerance and GEM clocks with +/- 100 ppm tolerance. If the tool unable to derive these with a set of input clocks then it generates a DRC.
  • Tool generates SDIO ref clock and SD DLL clocks as mentioned below:
    • In auto mode, fixed 200 MHz for SDIO0/1 and 1200 MHz for SD DLL.
    • In manual mode, DRC is provided if you are not using the same PLL for SD DLL and SDIO0/1 ref clock.
    • In manual mode, DRC is provided if SD DLL ref clock is not = 6 times SDIO0/1 ref clock.
Figure 1. Output Clocks