NoC Interfaces - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

The following is the list of interfaces between PS/PMC and NoC. You can select these in the NoC interfaces section to communicate with the DDR/PL/AIE.

Coherent (CCI) master ports
The CIPS IP core has four coherent master ports (FPD_CCI_NOC_0, 1, 2, 3) connected from PS-CCI to NoC. CCI drives these ports in interleaving mode (2 ports and 4 ports), so you must connect all 4 ports to the NoC to access any slave. The CIPS core masters A72/R5/PMC/DMA can make use of these ports. Also, PL masters that are connected to CIPS on the CCI slave ports can access these ports.
Note: The CCI master ports are interleaved and all four should be connected to the same instance of the logical NoC IP.
Non-Coherent (NCI) master ports
The CIPS core has two non-Coherent master ports (FPD_AXI_NOC_0,1). Only PL masters which are connected to NCI slave ports of the CIPS core can access these ports.
Tip: Coherency is NOT enabled by default at boot on the CCI AXI4-Lite ports.
LPD (RPU) master port
There is one master port from LPD (NOC_LPD_AXI_0) to NoC. LPD masters RPU/DMA can make use of this master port to access slaves.
PMC master port
The CIPS core has one master port (PMC_NOC_AXI_0) from PMC domain to NoC. This port is used by PMC for debug/boot.
CPM4/5 master ports
Two master ports (IF_PS_NOC_PCIE_0,1) are exposed from the CIPS core. One is connected to controller 0 and the other is to CCIX module. CPM4/5 can access DDR/PL/AIE regions using these ports. You can select connected ports in the CPM4/5 Configuration page.
DDRMC HSM1 Clock Port
Enables showing the dedicated DDRMC HSM1 clock on the IP Integrator canvas.
Coherent (CCI) Slave ports
The CIPS core has two coherent slave ports (NOC_FPD_CCI_0,1). Masters connected to these ports can achieve coherency and virtualization. Masters connected to these ports can access DDR, PL slaves which are connected to CIPS via CCI ports. Also, PL masters have access to CIPS internal memory regions.
Non-Coherent (NCI) Slave ports
The CIPS core has two non-coherent slave ports (NOC_FPD_AXI_0,1). Masters connected to these ports can achieve only virtualization. PL masters connected to these ports can access DDR, PL slaves which are connected to CIPS via NCI ports. Also, PL masters have access to CIPS internal memory regions.
PMC/LPD Slave port
There is one slave port (NOC_PMC_AXI_0) to LPD/PMC region. PL masters connected to this port get access to these regions.
CPM4/5 Slave port
The CIPS core has one NoC slave port (IF_NOC_PS_PCIE_0) connected to CPM4/5 module. External masters can connect to this port to configure the CPM4/5. You can select this port in the CPM4/5 Configuration page.

Figure 1 shows different NoC master/slave port options to enable these ports. The following table shows the addresses you can assign to DDR/AI Engine/PL slaves that are connected to CIPS master NoC ports. For more information on NoC address ranges and configuration, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

Table 1. NoC Region Address
Slave Region Start Address Size
DDR Low0 0x0 2 GB
Low1 0x800000000 32 GB
Low2 0xC000000000 256 GB
Low3 0x10000000000 734 GB
CH1 0x50000000000 1 TB
CH2 0x60000000000 1 TB
CH3 0x70000000000 1 TB
PL PLNOC2 TB 0x20100000000 2044 GB
PLNOC8 TB 0x80000000000 8 TB
AI Engine AIE_0 0x20000000000 4 TB

The following figures describe CIPS + DDR + PL slave connections on NoC:

Figure 1. CIPS NoC

When the CIPS IP is connected to the NoC IP block, the lowest latency connectivity to the hardened memory controllers (DDRMC) is fixed and listed in the following table:

Table 2. Lowest Latency Connectivity to the DDRMC
CIPS IP Port Name NoC Type Optimal DDRMC Port Selection in NoC IP
FPD_CCI_NOC_0 ps_cci 3
FPD_CCI_NOC_1 ps_cci 2
FPD_CCI_NOC_2 ps_cci 0
FPD_CCI_NOC_3 ps_cci 1
FPD_AXI_NOC_0 ps_nci 1
FPD_AXI_NOC_1 ps_nci 0
LPD_AXI_NOC_0 ps_rpu 3
PMC_NOC_AXI_0 ps_pmc 2
CPM_PCIE_NOC_0 ps_pcie 3
CPM_PCIE_NOC_1 ps_pcie 2
Figure 2. NoC IP Connectivity Tab for Lowest Latency Connectivity to the DDRMC

Figure 3. NoC General Configuration

Figure 4. NoC Slave Ports Configuration

Figure 5. NoC Master Ports Configuration

Figure 6. NoC Connectivity Configuration