Navigating Content by Design Process - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All AMD Versal™ adaptive SoC design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:

Hardware, IP, and Platform Development​
Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the AMD Vivado™ timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include: