MIO Ports - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

In the AMD Versalâ„¢ design tools, Control, Interfaces and Processing System IP core is used to configure the core Multi-Use IO (MIO) ports. There are up to 78 MIO ports available from the CIPS IP core. This core allows you to choose the different peripheral ports to be connected to the MIO ports.

Extended MIO Ports

Because there are only up to 78 MIO ports available, many peripheral I/O ports beyond these can still be routed to the programmable logic through the Extended MIO (EMIO) interface. Alternative routing for IOP interfaces through programmable logic enables you to take full advantage of the IOP available in the CIPS IP core. The Versal CIPS IP core allows you to select GPIO up to 96 signals. The Versal CIPS IP core has control logic to adjust user-selected width to flow into CIPS IP core.

Important: The EMIO signals for I2C, SPI flash memory, Gigabit Ethernet Management Data Input/Output (MDIO), SD/eMMC, GPIO 3-state enable signals are inverted in the Versal CIPS IP core.