IP Facts - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family AMD Versal™ adaptive SoC
Supported User Interfaces AXI4, AXI4-Lite, AXI4-Stream, Native, and NoC
Provided with Core
Design Files Verilog
Example Design Refer block automation for DDR/CPM reference designs
Test Bench N/A
Constraints File N/A
Simulation Model N/A
Supported S/W Driver N/A
Tested Design Flows
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Synthesis
Support
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.
  2. For the supported versions of the tools, see Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).