Core Overview - 3.3 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2023-05-16
Version
3.3 English

The Control Interfaces and Processing System IP core instantiates, boots, and configures the processing system section of the AMD Versal™ platform.

CIPS is designed as a hierarchical IP encapsulating two sub-IPs namely PS-PMC and CPM IPs. Designing for AMD Versal™ device always requires at the least the PMC involvement and therefore CIPS to be configured.