Transceiver Interface Ports - 3.3 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

The following table shows the transceiver I/O ports.

Table 1. Transceiver I/O
Name	I/O	Clock Domain	Description
GT_reset	I	Async	Active-High reset for the transceiver startup FSM. Note that this signal also initiates the reset sequence for the entire 10G/25G Ethernet IP core.
refclk_n0	I	Refer to Clocking.	Differential reference clock input for the SerDes, negative phase.
refclk_p0	I	Refer to Clocking.	Differential reference clock input for the SerDes, negative phase.
rx_serdes_data_n0	I	Refer to Clocking.	Serial data from the line; negative phase of the differential signal.
rx_serdes_data_p0	I	Refer to Clocking.	Serial data from the line; positive phase of the differential signal.
tx_serdes_data_n0	O	Refer to Clocking.	Serial data to the line; negative phase of the differential signal.
tx_serdes_data_p0	O	Refer to Clocking.	Serial data to the line; positive phase of the differential signal.
tx_serdes_clkout	O	Refer to Clocking.	When present, same as tx_clk_out.