Configuration Tab - 3.3 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2020-12-16
Version
3.3 English

The Configuration tab provides the basic core configuration options. Default values are pre-populated in all fields.

Figure 1. Configuration Tab (Versal)
Figure 2. Configuration Tab (UltraScale/UltraScale+)
Table 1. Configuration Options
Option Values Default
General
Select Core

Ethernet MAC 64-bit

Ethernet PCS/PMA 32-bit

Ethernet PCS/PMA 64-bit

Ethernet MAC+PCS/PMA 32-bit

Ethernet MAC+PCS/PMA 64-bit

 Ethernet MAC+PCS/PMA 64-bit
Speed

25.7812G

10.3125G

 25.7812G
Runtime Switchable Mode 0, 1 0
Num of Cores 9

1

2

3

4

 1
Clocking Asynchronous Asynchronous
Data Path Interface

AXI4-Stream 1

Media Independent Interface (MII) 2

AXI4-Stream
PCS/PMA 32-bit
Enable Preemption 802.3br Feature 0, 1 0
PCS/PMA Options
Base-R Base-KR

Base-R

Base-KR

 Base-KR
Include FEC Logic
Clause 74 (BASE-KR FEC) 3 6 0,1 0
Clause 108 (RS-FEC) 4 0,1 0
Clause 108 (Soft RS-FEC Tx, Hard RS-FEC Rx) 8 0,1 0
Auto-Negotiation/Link Training Logic
Auto-Negotiation/Link Training Logic

None

Include AN/LT Logic

 None
Control and Statistics Interface
Control and Statistics interface

Control and Status Vectors

Include AXI4-Lite

Control and Status Vectors
Include Statistics Counters 5 0,1 1
Statistics Resource Type 7 Registers, Block RAM Register
  1. The AXI4-Stream interface is visible and is the only option for the Ethernet MAC+PCS/PMA and standalone Ethernet MAC core.
  2. The MII interface is visible and is the only option for the Ethernet PCS/PMA core.
  3. Clause 74 (BASE-KR FEC) logic is not supported for Base-R.
  4. Clause 108 (RS-FEC) is not supported for Base-R,10G speed.
  5. The Statistics Counters are available in the register map only when you enable the Include Statistics Counters option. Otherwise, the Statistics Counters will not be available.
  6. Clause 74 (BASE-KR FEC) and Clause 108 (RS-FEC) both can be selected in Vivado IDE but during functional operation only one can be enabled at a time using the respective control signals.
  7. Statistics Resource Type Block RAM option will be provided in the future release.
  8. Soft RS-FEC TX, Hard RS-FEC RX option to reduce logic utilization by leveraging the embedded 100G RS-FEC function that exists within the CMAC block in UltraScale+™ devices.
  9. The Number of Cores will be 1 only for the Versal™ devices and multi-core support will not be supported as GT will always be in the example design/outside the core.