| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| ts_clk | IN | N/A | It is a free running clock which clocks system timer’s counters |
| ts_rst | IN | ts_clk | System timer reset active-High |
| tod_intr | OUT | ts_clk | Interrupt asserted on 1-PPS event |
| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| ts_clk | IN | N/A | It is a free running clock which clocks system timer’s counters |
| ts_rst | IN | ts_clk | System timer reset active-High |
| tod_intr | OUT | ts_clk | Interrupt asserted on 1-PPS event |