AXI4 Interface User Logic - 3.3 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2020-12-16
Version
3.3 English

The following sections provide the AXI4-Lite interface state machine control and ports.

User State Machine

The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown below:

Figure 1. User State Machine for AXI4-Lite Interface

A functional description of each state is described as below:

IDLE_STATE
By default the FSM will be in IDLE_STATE. When the user_read_req signal becomes High, then it moves to the READ_STATE else if the user_write_req signal is High, it moves to WRITE_STATE else it remains in IDLE_STATE.
WRITE_STATE
You provide S_AXI_AWVALID, S_AXI_AWADDR, S_AXI_WVALID, S_AXI_WDATA and S_AXI_WSTRB in this state to write to the register map through AXI. When S_AXI_BVALID and S_AXI_BREADY from the AXI slave are High then it moves to ACK_STATE. If any write operation happens in any illegal addresses, the S_AXI_BRESP[1:0] indicates 2'b10 that asserts the write error signal.
READ_STATE
You provide S_AXI_ARVALID and S_AXI_ARADDR in this state to read from the register map through AXI. When S_AXI_RVALID and S_AXI_RREADY are High then it moves to ACK_STATE. If any read operation happens from any illegal addresses, the S_AXI_RRESP[1:0] indicates 2'b10 that asserts the read error signal.
ACK_STATE
The state moves to IDLE_STATE.

AXI User Interface Ports

Table 1. AXI User Interface Ports
Name Size I/O Description
S_AXI_ACLK 1 I AXI clock signal
S_AXI_ARESETN 1 I AXI active-Low synchronous reset
S_AXI_PM_TICK 1 I PM tick user input
S_AXI_AWADDR 32 I AXI write address
S_AXI_AWVALID 1 I AXI write address valid
S_AXI_AWREADY 1 O AXI write address ready
S_AXI_WDATA 32 I AXI write data
S_AXI_WSTRB 4 I AXI write strobe. This signal indicates which byte lanes hold valid data.
S_AXI_WVALID 1 I AXI write data valid. This signal indicates that valid write data and strobes are available.
S_AXI_WREADY 1 O AXI write data ready
S_AXI_BRESP 2 O

AXI write response. This signal indicates the status of the write transaction.

'b00 = OKAY

‘b01 = EXOKAY

‘b10 = SLVERR

‘b11 = DECERR
S_AXI_BVALID 1 O AXI write response valid. This signal indicates that the channel is signaling a valid write response.
S_AXI_BREADY 1 I AXI write response ready.
S_AXI_ARADDR 32 I AXI read address
S_AXI_ARVALID 1 I AXI read address valid
S_AXI_ARREADY 1 O AXI read address ready
S_AXI_RDATA 32 O AXI read data issued by slave
S_AXI_RRESP 2 O

AXI read response. This signal indicates the status of the read transfer.

‘b00 = OKAY

‘b01 = EXOKAY

‘b10 = SLVERR

‘b11 = DECERR
S_AXI_RVALID 1 O AXI read data valid
S_AXI_RREADY 1 I AXI read ready. This signal indicates the user/master can accept the read data and response information.

Valid Write Transactions

Figure 2. AXI4-Lite User-Side Write Transaction

Invalid Write Transactions

Figure 3. AXI4-Lite User Side Write Transaction with Invalid Write Address

Valid Read Transactions

Figure 4. AXI4-Lite User Side Read Transaction

Invalid Read Transactions

Figure 5. AXI4-Lite User Side Read Transaction with Invalid Read Address