10G/25G Runtime Switchable IP features - 3.3 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

Complete MAC and PCS features
Base-KR mode based on IEEE 802.3 Clause 49
Statistics and Diagnostics
66-bit SerDes interface using Xilinx GTY transceiver
Custom preamble and adjustable InterFrame Gap
Pause Processing
64-bit AXI4-Stream interface
Optional Clause 73 Auto-negotiation
Optional Clause 72 Link Training
Optional Clause 74 FEC
Supports gt_refclk frequency 161.1328125 MHz only

Table 1. Feature Compatibility Matrix (GTY)
Variant	User Interface	MAC	PCS	Pause Processing	Auto- Negotiation and Link Training	Clause 74 FEC	Clause 108 RS-FEC	IEEE 1588 Time Stamp
10G MAC with PCS	64-bit AXI4-Stream	X	X	X	X	X		X
Low Latency 10G MAC with PCS	64-bit AXI4-Stream	X	X
Low Latency 10G MAC with PCS	32-bit AXI4-Stream	X	X		X ²
Low Latency 25G MAC with PCS	64-bit AXI4-Stream	X	X
25G MAC with PCS	64-bit AXI4-Stream	X	X	X	X	X	X	X
Runtime switchable 10G/25G MAC+PCS	64-bit AXI4-Stream	X	X	X	X	X	X	X
10G PCS-only	XGMII		X		X	X		X ¹
25G PCS-only	25GMII		X		X	X	X	X ¹
Runtime switchable 10/25G PCS-only	XGMII/ 25GMII		X		X	X	X	X ¹
10G MAC-only	64-bit AXI4-Stream	X		X
Preemption (802.1CM) 10G/25G only	64-bit AXI4-Stream	X	X					X
Only 2-step timestamping is supported with the PCS-only configurations. Only auto-negotiation logic.

Table 2. Feature Compatibility Matrix (GTM)
Variant	User Interface	MAC	PCS	Pause Processing	Auto- Negotiation and Link Training	Clause 74 FEC	Clause 108 RS-FEC	IEEE 1588 Time Stamp
10G MAC with PCS	64-bit AXI4-Stream	X	X	X		X		X
Low Latency 10G MAC with PCS	64-bit AXI4-Stream	X	X
Low Latency 25G MAC with PCS	64-bit AXI4-Stream	X	X
25G MAC with PCS	64-bit AXI4-Stream	X	X	X		X	X	X
10G PCS-only	XGMII		X			X		X ¹
25G PCS-only	25GMII		X			X	X	X ¹
Preemption (802.CM) 10G/25G only	64-bit AXI4-Stream	X	X					X
Only 2-step timestamping is supported with the PCS-only configurations.