Multiple Cores (2x50G) - Asynchronous Clock Mode GTY (2x25G) for UltraScale/UltraScale+ Device - Multiple Cores (2x50G) - Asynchronous Clock Mode GTY (2x25G) for UltraScale/UltraScale+ Device - 3.2 English - PG211
40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
- Document ID
- PG211
- Release Date
- 2021-10-27
- Version
- 3.2 English
Figure 1. Multiple Cores (2x50G) - Asynchronous Clock Mode GTY (2x25G) for
UltraScale/UltraScale+ Device
