| LogiCORE™ IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family |
Versal® ACAP Zynq® UltraScale+™ RFSoC Zynq® UltraScale+™ MPSoC Virtex® UltraScale+™ Kintex® UltraScale+™ Kintex® UltraScale™ |
| Supported User Interfaces |
128-bit Straddle Packet AXI4-Stream for 50 Gb/s 128-bit Straddle Packet or 256-bit AXI4-Stream for 40 Gb/s |
| Resources | Performance and Resource Use web page |
| Provided with Subsystem | |
| Design Files | Encrypted RTL |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Verilog |
| Supported S/W Driver | Not Applicable |
| Tested Design Flows 1 | |
| Design Entry | Vivado® Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Synopsys or Vivado synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54690 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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