Configuration Tab - Configuration Tab - 3.2 English - PG211

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
Document ID
PG211
Release Date
2021-10-27
Version
3.2 English

The Configuration tab provides the basic core configuration options.

Default values are pre-populated in all tabs.

Figure 1. Configuration Tab for UltraScale/UltraScale+
Figure 2. Configuration Tab for Versal ACAP
Table 1. Configuration Options
Option Values Default
General
Select Core Ethernet MAC+PCS/PMA Ethernet PCS/PMA Ethernet MAC+PCS/PMA
Speed 50G

40G

 50G
Number of Cores 1

2

 1
Clocking Synchronous Asynchronous Asynchronous
Runtime Switchable Mode 0,1 0
Data Path Interface 128-bit Straddled AXI4-Stream 1

256-bit Regular AXI4-Stream 2

MII 3

128-bit Straddled AXI4-Stream
PCS/PMA Options
Base-R

Base-KR

 Base-R

Base-KR

 Base-KR
Include FEC Logic
Clause 74 (BASE-KR FEC) 4 6 0,12 mi 0
Clause 91 (RS-FEC) 5 6 0,1 0
KP4 FEC with Transcode 7 0,1 0
Soft RS-FEC (544,514) 0,1 0
Auto Negotiation/Link Training Logic
Auto Negotiation/Link Training Logic None

Include AN/LT Logic

 None
Control and Statistics Interface
Control and Statistics interface Control and Status Vectors Include AXI4-Lite Control and Status Vectors
Include Statistics Counters 0,1 8 1
Statistics Resource Type Register, block RAM 9 block RAM
  1. The 128-bit Straddled AXI4-Stream is visible and option for Ethernet MAC+PCS/PMA with 40G and 50G line rate options.
  2. The 256-bit Regular AXI4-Stream is visible and option for Ethernet MAC+PCS/PMA with 40G Line rate only.
  3. The MII interface is visible and is the only option for the Ethernet PCS/PMA core.
  4. Clause 74 (BASE-KR FEC) logic is not supported for Base-R.
  5. Clause 91 (RS-FEC) is not supported for Base-R, 40G speed.
  6. Clause 74 (BASE-KR FEC) and Clause 91 (RS-FEC) both can be selected in Vivado® IDE but during functional operation only one can be enabled at a time using the respective control signals.
  7. GTM integrated hard FEC. Only applicable for Devices with GTM (Not applicable for Versal® ACAP).
  8. The Statistics Counters are available in the register map only when you enable the Include Statistics Counters option. Otherwise, the Statistics Counters are not available.
  9. Statistics Resource Type block RAM option will be provided in the future release.
  10. There is only single core support for Versal ACAP. Multi-core is not supported as the example design has GT outside the core.