Ports Added
The following ports have been added.
-
ctl_gt_reset_all_* -
ctl_gt_reset_* -
ctl_gt_rx_reset_* -
gt_reset_all_in_* -
gt_tx_reset_in_* -
gt_rx_reset_in_* -
ctl_an_fec_25g_rs_request -
ctl_an_fec_25g_baser_request -
stat_an_lp_fec_25g_rs_request -
stat_an_lp_fec_25g_baser_request -
tx_ptp_rxtstamp_in -
rx_ptp_pcslane_out_* -
ctl_an_fec_25g_baser_request_*
Ports Removed
stat_tx_underflow_err
Port Changes
-
rx_serdes_reset_done_in_*torx_serdes_reset_*. - SERDES_WIDTH with 64 for several I/O ports.
-
ctl_an_ability_25gbase_crtoctl_an_ability_25gbase_krcr -
ctl_an_ability_25gbase_krtoctl_an_ability_25gbase_krcr_s -
ctl_an_fec_requesttoctl_an_fec_10g_request. Updated description. -
stat_rx_errored_block_increment_validtostat_rx_bad_code_valid -
stat_rx_bad_sh_increment_0[3:0]tostat_rx_framing_err_0[3:0] -
stat_rx_bad_sh_increment_1[3:0]tostat_rx_framing_err_1[3:0] -
stat_rx_bad_sh_increment_2[3:0]tostat_rx_framing_err_2[3:0] -
stat_rx_bad_sh_increment_3[3:0]tostat_rx_framing_err_3[3:0] -
stat_rx_bad_sh_increment_valid_1tostat_rx_valid_1 -
stat_rx_bad_sh_increment_valid_2tostat_rx_valid_2 -
stat_rx_bad_sh_increment_valid_3tostat_rx_valid_3 -
rx_axis_tuser_0torx_axis_tuser_*
Hex Addresses Added
- CONFIGURATION_LT_SEED_REG1: 0114
- CONFIGURATION_LT_COEFFICIENT_REG1: 0134
- STAT_LT_COEFFICIENT1_REG: 0478
- STAT_RX_ERROR_LSB: 0668
- STAT_RX_ERROR_LSB: 066C
Signals Added to Register Definitions
-
ctl_gt_rx_reset -
ctl_gt_tx_reset -
ctl_tx_ipg_value -
ctl_tx_custom_preamble_enable -
ctl_rx_custom_preamble_enable -
ctl_an_fec_25g_rs_request -
ctl_an_fec_25g_baser_request -
stat_an_lp_fec_25g_rs_request -
stat_an_lp_fec_25g_baser_request
Register Tables Added
- CONFIGURATION_LT_SEED_REG1: 0114
- CONFIGURATION_LT_COEFFICIENT_REG1: 0134
- STAT_LT_COEFFICIENT1_REG: 0478
- STAT_RX_ERROR_LSB: 0668
- STAT_RX_ERROR_MSB: 066C