The primary datapath interface to the DCMAC Subsystem is a high-performance segmented AXI4-Stream interface. Transmit and receive frame data is presented to and collected from this interface.
The following sections describe the AXI4-Stream signals and the signals to be used for each supported data rate. Different groups of signals are used by different data rates. Consequently, their interpretation by the user logic and the interface logic can differ. All unused input signals (including those inputs associated with unused or disabled modes) must be driven to 0.
The DCMAC Subsystem can be dynamically reconfigured during run-time to select a different mode of operation (changing the data rate for a port). In this case, the user logic must be configured carefully to properly drive the correct signals depending on the mode of operation.
All primary AXI4-Stream interface signals are
little endian as required by 7. This
includes all tdata and tuser signals
(tuser_sopN, tuser_eopN,
tuser_mtyN, and tuser_errN). The exceptions are
the tx/rx_preamble signals which are formatted as big
endian. For more information, see the Interface Endianness
section.