INPUT_ADDR - 3.0 English - UG1563

Vitis AI RNN User Guide (UG1563)

Document ID
UG1563
Release Date
2023-01-12
Version
3.0 English

The input_addr register is used to indicate the DDR address of input activations. The details of the input_addr register are shown in the following table.

Bit Register Address R/W Description
31:0 INPUT_ADDR_H 0x28 R/W The higher 32 bits of input address in DDR. It is shared with the high output address register.
31:0 INPUT_ADDR_L 0x2C R/W The lower 32 bits of input address in DDR.