System Clocks - System Clocks - 3.0 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document_ID
PG369
Release_Date
2025-06-11
Version
3.0 English

The abp3_clk signal is a mandatory clock which must be present and stable in all modes of operation. It is used for internal configuration and synchronization functions in addition to its use as a clock for the processor interface.