GT Reset Control Ports - GT Reset Control Ports - 3.0 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2025-06-11
Version
3.0 English
Table 1. GT Reset Controls Ports
Port Name I/O Description
gtwiz_reset_all_in <0-5> I Multi-bit reset input to the GT Reset IPs for Multi-Quad control. It resets the PLL and datapath of GT.
gt_reset_tx_datapath_in_<0-23> I TX reset datapath input to the GT Reset IP.
gt_reset_rx_datapath_in_<0-23> I RX reset datapath input to the GT Reset IP.
gt_tx_reset_done_out_<0-23> O TX Reset Done output from the GT Reset IP.
gt_rx_reset_done_out_<0-23> O RX Reset Done output from the GT Reset IP.
  1. These ports are applicable for Legacy GT Wizard only.
  2. You can control the gtwiz_reset_all_in based on the configuration and the number of Quads individually. For example, for NRZ configurations, each quad can be controlled by each bit of reset input. For PAM4, each dual can be controlled by each bit. The operation of reset should be based on the configuration selected, similar to the Assertion and Deassertion of DCMAC Resets section.