Flex Interface - Flex Interface - 3.0 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2025-06-11
Version
3.0 English

This section describes the flex interface (FLEX I/F) signals. The following tables define the signal description section, the direction, and meaning of the various signals. The subsequent sections describes how the signals are hooked up for the various port rates.

Note: In these tables, <N> = port number 0-5.
Table 1. Flex Interface Signal Descriptions: TX Direction
Port Name Clock Domain I/O Description
tx_flex_ena_<N> tx_flexif_clk[<N>] I Indicates valid data.
tx_flex_enab_<N> tx_flexif_clk[<N>] I Reserved (not currently used).
tx_flex_start_<N> tx_flexif_clk[<N>] I Indicates cycle at start of RS-FEC codeword.
tx_flex_startb_<N> tx_flexif_clk[<N>] I Indicates cycle at start of RS-FEC codeword. This signal is for 50G FEC-only mode and for 100G KR4 FEC-only mode. The data for this port is split. The lower 160 bits use tx_flex_start as normal. The upper 160 bits use tx_flex_startb.
tx_flex_amflag_0 tx_flexif_clk[0] I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_flex_amflag_1 tx_flexif_clk[0]

tx_flexif_clk[1]

 I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_flex_amflag_2 tx_flexif_clk[0]

tx_flexif_clk[2]

 I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_flex_amflag_3 tx_flexif_clk[0]

tx_flexif_clk[2]

tx_flexif_clk[3]

 I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_flex_amflag_4 tx_flexif_clk[4] I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_flex_amflag_5 tx_flexif_clk[4]

tx_flexif_clk[5]

 I Indicates that the flex input data includes alignment marker blocks. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
tx_ptp_flex_tag_field_in_<N>[7:0] tx_flexif_clk[<N>] I Unique identifier for PTP packet which can be used to match TX timestamps with a specific packet. This will match the output tag on tx_ptp_tstamp_tag_out.
tx_ptp_flex_1588loc_in_<N>0[2:0] tx_flexif_clk[<N>] I Selects the lane which the timestamp must be taken from. In cases where more than eight lanes are possible (400GE in DCMAC), it is possible to have more than one timestamped packet. In this case, the tx_ptp_flex_1588loc_in for each set of 8 lanes (tx_ptp_flex_1588loc_in_0 and tx_ptp_flex_1588loc_in_2 for DCMAC 400GE FLEX I/F) is used to indicate the start of the timestamped packet.
tx_ptp_flex_1588op_in_<N> tx_flexif_clk[<N>] I Indicates that a TX timestamp is requested on this cycle.
tx_flex_stall_<N> tx_flexif_clk[<N>] O When asserted, stall sending additional data. Response to stall can take up to two tx_flexif_clk cycles.
tx_flex_data_0[329:0] tx_flexif_clk[0] I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
tx_flex_data_1[329:0] tx_flexif_clk[0]

tx_flexif_clk[1]

 I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
tx_flex_data_2[329:0] tx_flexif_clk[0]

tx_flexif_clk[2]

 I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
tx_flex_data_3[329:0] tx_flexif_clk[0]

tx_flexif_clk[2]

tx_flexif_clk[3]

 I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
tx_flex_data_4[319:0] tx_flexif_clk[4] I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
tx_flex_data_5[319:0] tx_flexif_clk[4]

tx_flexif_clk[5]

 I FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the control signals from the first lane are needed.
Table 2. Flex Interface Signal Descriptions: RX Direction
Port Name Clock Domain I/O Description
rx_flex_ena_<N> rx_flexif_clk[<N>] O Indicates valid data. For 50G FEC-only mode, both 50G have the same enable pattern.
rx_flex_amflag_0 rx_flexif_clk[0] O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_amflag_1 rx_flexif_clk[0]

rx_flexif_clk[1]

 O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_amflag_2 rx_flexif_clk[0]

rx_flexif_clk[2]

 O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_amflag_3 rx_flexif_clk[0]

rx_flexif_clk[2]

rx_flexif_clk[3]

 O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_amflag_4 rx_flexif_clk[4] O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_amflag_5 rx_flexif_clk[4]

rx_flexif_clk[5]

 O Either indicates alignment marker itself (in modes where AM is output), or the first cycle after the AM. This signal is valid for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
rx_flex_lane0_0 rx_flexif_clk[0] O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_flex_lane0_1 rx_flexif_clk[0]

rx_flexif_clk[1]

 O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_flex_lane0_2 rx_flexif_clk[0]

rx_flexif_clk[2]

 O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_flex_lane0_3 rx_flexif_clk[0]

rx_flexif_clk[2]

rx_flexif_clk[3]

 O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_flex_lane0_4 rx_flexif_clk[4] O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_flex_lane0_5 rx_flexif_clk[4]

rx_flexif_clk[5]

 O Indicates data on virtual lane 0 occurs on this cycle (in first data lane).
rx_ptp_tstamp_out_<N>[31:0] rx_flexif_clk[<N>] O Timestamp of the PTP packet with 2-8 ns granularity. Note, the upper bits is omitted to reduce the number of output pins.
rx_flex_start_<N> rx_flexif_clk[<N>] O Indicates cycle at start of RS-FEC codeword.
rx_flex_startb_<N> rx_flexif_clk[<N>] O In 50G FEC-only and 100G RS(528,514) FEC-only modes:
  • Indicates cycle at start of RS-FEC codeword. The data for this port is split.
  • The lower 160 bits use rx_flex_start as normal. The upper 160 bits use rx_flex_startb.

In PCS-only, 128GFC, and FlexO modes:

  • Indicates RX status (e.g., in PCS mode, a value of 1 indicates the PCS is aligned and not in hi_ber state).
  • Can be used to switch to a locally timed and generated local fault.
rx_flex_fec_rx_dout_flags_<N>[3:0] rx_flexif_clk[<N>] O Flags for FEC-only mode.

The bits are interpreted as follows:

  • 0: Indicates that the syndromes were zero
  • 1: Indicates that the syndromes were non-zero
  • 2: Indicates that the number of errors in the codeword did not exceed the FEC's error correction capability
  • 3: Indicates that the number of errors in the codeword exceeded the FEC’s error correction capability
rx_flex_fec_rx_dout_flagsb_<N>[3:0] rx_flexif_clk[<N>] O Flags for upper 50G FEC-only mode.

The bits are interpreted as follows:

  • 0: Indicates that the syndromes were zero
  • 1: Indicates that the syndromes were non-zero
  • 2: Indicates that the number of errors in the codeword did not exceed the FEC's error correction capability
  • 3: Indicates that the number of errors in the codeword exceeded the FEC’s error correction capability
rx_flex_data_0[329:0] rx_flexif_clk[0] O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.
rx_flex_data_1[329:0] rx_flexif_clk[0]

rx_flexif_clk[1]

 O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.
rx_flex_data_2[329:0] rx_flexif_clk[0]

rx_flexif_clk[2]

 O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.
rx_flex_data_3[329:0] rx_flexif_clk[0]

rx_flexif_clk[2]

rx_flexif_clk[3]

 O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.
rx_flex_data_4[319:0] rx_flexif_clk[4] O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.
rx_flex_data_5[319:0] rx_flexif_clk[4]

rx_flexif_clk[5]

 O FLEX I/F data. For 200GE/400GE, data buses are grouped (200GE: 0/1, 2/3, 4/5; 400GE: 0/1/2/3). For 200GE/400GE, only the flag signals from the first lane are indicated.