Timer Syncer IP Interface Ports - 3.0 English

Timer Syncer IP Interface Ports - 3.0 English - PG314

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID

PG314

Release Date

2024-11-13

Version

3.0 English

Below are the Timer Syncer IP top level ports.

Table 1. Timer Sync IP Top Level Ports
Signal	Direction	Clock Domain	Description
Clock Resets
ts_clk	IN	N/A	Free running clock which clocks the System Timer’s counters
ts_rst	IN	ts_clk	System timer reset -active High
tod_intr	OUT	ts_clk	Interrupt asserted on 1-PPS event
External ToD Bus Interface
tod_1pps_in	IN	N/A	External Bus 1-PPS input
tod_sec_clk_in	IN	N/A	External Bus clock, used for tod_sec_in
tod_sec_in	IN	tod_sec_clk_in	External Bus seconds serial data
tod_1pps_out	Output	ts_clk	1-PPS output. Asserted when the System Timer’s nano-second field rolls-over.
tod_sec_clk_out	IN	N/A	Echo of External Bus clock
tod_sec_out	IN	tod_sec_clk_in	Serial output of internal ToD seconds
Per-Port Port Timer Interface _m denotes the port number (0 ≤ m ≤ 15)
tx_phy_clk_m	IN		Port TX PHY Clock
rx_phy_clk_m	IN		Port RX PHY Clock
tx_phy_rst_m	IN	tx_phy_clk_m	Port TX Reset
rx_phy_rst_m	IN	rx_phy_clk_m	Port RX Reset
tx_tod_sec_m[47:0]	OUT	tx_phy_clk_m	Port TX Timer seconds field
tx_tod_ns_m[31:0]	OUT	tx_phy_clk_m	Port TX Timer nano-seconds field
tx_tod_corr_m[63:0]	OUT	tx_phy_clk_m	Port TX Timer CF field
rx_tod_sec_m[47:0]	OUT	rx_phy_clk_m	Port RX Timer seconds field
rx_tod_ns_m[31:0]	OUT	rx_phy_clk_m	Port RX Timer nano-seconds field
rx_tod_corr_m[63:0]	OUT	rx_phy_clk_m	Port RX Timer CF field
AXI4-Lite Interface
s_axi_aclk	IN		AXI4-Lite I/F clock
s_axi_aresetn	IN	s_axi_aclk	AXI4-Lite I/F reset
s_axi_awaddr[31:0]	IN	s_axi_aclk	Write address
s_axi_awvalid	IN	s_axi_aclk	Write Address Valid
s_axi_awready	OUT	s_axi_aclk	Write Address Ready
s_axi_wdata[31:0]	IN	s_axi_aclk	Write Data
s_axi_wstrb[3:0]	IN	s_axi_aclk	Write Data Byte Valid. Tie to 4’hF
s_axi_wvalid	IN	s_axi_aclk	Write Valid
s_axi_wready	OUT	s_axi_aclk	Write Ready
s_axi_bresp	OUT	s_axi_aclk	Write Response
s_axi_bvalid	OUT	s_axi_aclk	Write Response Valid
s_axi_bready	IN	s_axi_aclk	Write Response Ready
s_axi_araddr[31:0]	IN	s_axi_aclk	Read Address
s_axi_arvalid	IN	s_axi_aclk	Read Address Valid
s_axi_arready	OUT	s_axi_aclk	Read Address Ready
s_axi_rdata[31:0]	OUT	s_axi_aclk	Read Data
s_axi_rresp	OUT	s_axi_aclk	Read Response
s_axi_rvalid	OUT	s_axi_aclk	Read Data Valid
s_axi_rready	IN	s_axi_aclk	Read Ready