Prerequisites - Prerequisites - 3.0 English - PG278

There are certain requirements that must be fulfilled when programming the core.

• The core does not contain a data realignment engine; therefore, the application software must align the memory address before writing to the register. The alignment requirement is specified below. This ensures the start address is aligned with the width of the memory interface.
  Note: The start address should be aligned with: (8 * Pixels per Clock) Bytes.
• The Stride value (in bytes) must be aligned as above to make sure that every row of pixels starts at an aligned memory location. Use the following equation to compute the stride from the width (in pixels) in raster-scan order:
  Stride in Bytes ≥ (Width × Bytes per Pixel);

  The bytes per pixel value varies per video in memory format, and is described in Memory Mapped AXI4 Interface.

  Use the following equation to compute the stride from the width (in pixels) in tile-scan order for a tile size of n × 4 (where n = 32 or 64):

  Stride in Bytes >= (((Width + (n-1)) & ~(n-1)) * 4 * bit-depth) / 8
  Note:

  • Due to a current limitation of the IP core when configured for samples per clock=8, the minimum stride required for tiled video format with bit-depth=10 needs to be calculated using n=64 in the above formula for both 32x4 and 64x4 tiles.
  • Padding bytes is sometimes necessary (hence, the ≥ in the equation) to make sure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped interface as described in Stride (0x0020) Register.
• The Width value must be a multiple of Pixels per Clock as selected in the Vivado IDE for this core.
• For Tile video format, the Width value must be a multiple of four and Pixels per Clock. Height value must be multiple of eight.