Spartan UltraScale+ FPGA Overview - Spartan UltraScale+ FPGA Overview - 2025.2 English - XD332

SCU35 IO Technical Reference Design User Guide (XD332)

Document_ID
XD332
Release_Date
2026-08-20
Version
2025.2 English

The Spartan UltraScale+ device is an FPGA built on the 16 nm FinFET UltraScale architecture. The following figure shows a high-level block diagram of the device architecture.

Spartan UltraScale+ Block Diagram

Figure 1: Spartan UltraScale+ Block Diagram

The following summarizes the key features of the Spartan UltraScale+ device:

  • Memory Controller

  • Integrated PCIe® support

  • MIPI support

  • GTH Transceivers

  • Platform Management Controller (PMC)

  • High-Performance I/O (HPIO) with voltage support from 1.0V to 1.8V

  • High-Density I/O (HDIO) with voltage support from 1.2V to 3.3V