This chapter describes the reference design hardware architecture. The following figure shows the block diagram of the design component inside the PL.
Figure 3: SCU35 IO TRD Hardware Platform
At a high-level, the design divides into three subsystems:
Processor subsystem
MicroBlaze V
AXI interrupt controller
Local memory
AXI SmartConnect
AXI Timer
Peripherals subsystem
LEDs
PMODs
Push Buttons
DIP Switches
Accelerometer (iic_acl_main)
Electrically erasable programmable read-only memory (EPROM) (iic_eeprom_main)
INA700 (iic_ina_main)
UART interface
The processor subsystem consists of the MicroBlaze V soft processor and additional components ensuring its proper functioning and optimal performance. The MicroBlaze V processor is a highly configurable soft-core microprocessor offering flexibility for integration into FPGA-based designs. An AXI Interrupt Controller supports the processor, managing and prioritizing signals from various sources to allow the processor to efficiently handle both hardware and software events. A dedicated on-chip Local Memory complements the processor storing code and data which results in faster access times and lower latency compared to external memory sources. The AXI SmartConnect IP efficiently manages data transfers between the processor, memory, and peripheral components leveraging configurable AXI protocols for high-performance interconnectivity. Additionally, the AXI Timer module provides precise timing and interval measurements, supporting real-time operations and task scheduling.
The peripherals subsystem leverages AXI I2C and AXI GPIO interfaces connecting directly to the FPGA I/Os. These interfaces provide a unified means for communicating with the evaluation board’s various external components. The design routes signals from the FPGA pins directly to elements, such as LEDs, PMODs, push buttons, DIP switches, accelerometers, EEPROM, and INA700 devices, enabling streamlined and standardized access through the AXI protocols. This approach minimizes design complexity while enhancing scalability and ease of integration, ensuring that each device communicates efficiently with the core system.
The UART subsystem provides a dedicated communication channel between the processor and the host PC. This module sends and receives serial data during operation. By interfacing with the processor through the AXI SmartConnect, the UART subsystem ensures seamless integration and efficient data transfers throughout the system. This provides a reliable communication link for real-time interactions and command executions between the host and the processor.