The following table identifies the clocks in the hardware design, their source, frequency, and function.
Table 1: System Clocks
| Clock | Clock Source | Clock Frequency | Function |
|---|---|---|---|
| sys_diff_clock | TLSM2 (external) | 100 MHz | FPGA clock source for clocking wizard |
| microblaze_riscv_0_Clk | Clocking Wizard | 200 MHz | Clock source for all IPs in the design |
The TLSM2 oscillator on the SCU35 evaluation board provides the sys_diff_clock clock, which serves as the reference input clock for the Clocking Wizard instance inside the FPGA.
The Clocking Wizard instance generates the microblaze_riscv_0_Clk clock, deriving it from the sys_diff_clock, driving all the AXI interfaces and the MicroBlaze V subsystem.
Table 2: System and User Resets
| Reset | Reset Source | Purpose |
|---|---|---|
| reset | CPU-RST (external) | User reset to reset the system, including the peripheral, to their initial state |
| debug_sys_rst | MicroBlaze Debug Module (MDM) V | Debug reset to reset the system, including the peripheral, to their initial state |
| mb_reset | Processor System Reset | System reset to reset the MicroBlaze V core |
| bus_struct_reset | Processor System Reset | System reset to reset the local memory |
| peripheral_aresetn | Processor System Reset | Asynchronous system reset to reset the peripheral |
Use the reset and debug_sys_rst resets to reset the entire system. The reset connects to the CPU-RST button on the SCU35 evaluation board.
The Processor System Reset generates the three reset signals: mb_reset, bus_struct_reset, and peripheral_aresetn. The bus_struct_reset comes out of reset first, followed by the peripheral_aresetn reset, and then the mb_reset.