Step 1: Creating a Project with the Vivado New Project Wizard - Step 1: Creating a Project with the Vivado New Project Wizard - 2025.2 English - UG936

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2025-11-20
Version
2025.2 English
To create a project, use the New Project wizard to name the project, add RTL source files and constraints, and specify the target device.
  1. Invoke the Vivado IDE.
  2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
  3. In the Project Name page, name the new project proj_hdl and provide the project location (C:/Vivado_Debug). Ensure that the Create project subdirectory is selected. Click Next.
  4. In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
  5. In the Add Sources page:
    1. Set Target Language to VHDL.
    2. Click the “+” sign, and click Add Directories.
    3. In the Add Source Directories dialog box, navigate to the /src/lab2 directory, and choose the sine_high, sine_low, sine_mid, and ila_0 directories. Click Select.
    4. Verify that the directories are added, and Copy Sources into Project is selected.
    5. Click the “+” sign, and click Add File.
    6. In the Add Source Files dialog box, navigate to the/src/lab2 directory and choose debounce.vhd, fsn.vhd, sinegen.vhd, and sinegen_demo_inst.vhd files. Click OK.
    7. Verify that the sources and directories are added, and that Copy Sources into Project is selected. Click Next.
  6. In the Add Constraints dialog box, click the “+” sign, and click Add Files.
  7. Navigate to /src/lab1 directory and select sinegen_demo_kc705.xdc. Click Next.
  8. In the Default Part dialog box, specify the xc7k325tffg900-2 part for the KC705 platform. You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
  9. Review the New Project Summary page. Verify that the data appears as expected per the previous steps. Click Finish.
  10. In the Sources window in Vivado IDE, expand sinegen_demo_inst to see the source files for this lab.
    Note: ila_0 core is added to the project.


  11. Double-click the sinegen_demo_inst.vhd file, shown in the following figure to open it and inspect the instantiation and port mapping of the ILA core in the HDL code.