To create a project, use the New Project
wizard to name the project, to add RTL source files and constraints, and to specify the
target device.
- Invoke the Vivado IDE.
- In the Getting Started page, click Create Project to start the New Project wizard. Click Next.
- In the Project Name page, name the new project proj_netlist and provide the project location (C:/Vivado_Debug). Ensure that Create Project Subdirectory is selected and click Next.
- In the Project Type page, specify the type of project to create as RTL Project. Click Next.
- In the Add Sources page:
- Set Target Language to VHDL.
- Click the “+” sign, and click Add Files.
- In the Add Source Files dialog box, navigate to the /src/lab1 directory.
- Select all VHD source files, and click OK.
- Verify that the files are added, and Copy Sources into the project is selected.
- Click Add.
- In the Add Directories dialog box, navigate to the /src/lab1 directory.
- Select sine_high, sine_low, and sine_mid directories and click Select.
- Verify that the directories are added. Click Next.
- In the Add Constraints dialog box, click the “+” sign, and click Add Files.
- Navigate to /src/lab1 directory and select sinegen_demo_kc705.xdc. Click Next.
- In the Default Part dialog box, specify the xc7k325tffg900-2 part for the KC705 platform. You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
- Review the New Project Summary page. Verify that the data appears as
expected, per the previous steps, and click Finish.Note: It could take a moment for the project to initialize.