Review the user inter-clock uncertainty and reduce it to the minimum value needed. Avoid overconstraining beyond 0.5 ns. For more information, see UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).
Review the user inter-clock uncertainty and reduce it to the minimum value needed. Avoid overconstraining beyond 0.5 ns. For more information, see UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).