Resolution - Resolution - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2025-12-10
Version
2025.2 English
Because the waveforms do not allow safe timing analysis between the two clocks, treat these clocks as asynchronous. Cover the paths between the two clock domains with a timing exception such as:
set_max_delay -datapath_only ...
set_false_path ...
set_clock_groups ...