Resolution - Resolution - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2025-12-10
Version
2025.2 English

Remove the primary clock definition on the hierarchical pin. If a downstream clock is required, use a create_generated_clock constraint with the driver clock specified as the master clock instead.