Resolution - Resolution - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2025-12-10
Version
2025.2 English

Design the crossing path with proper synchronization. At minimum, add a double-register logic synchronizer on the capture clock side.

If a FIFO or higher-level protocol already exists on the path, this check can be safely ignored. For a detailed list of CDC violations, run report_cdc.