The DRC reports that a large hold violation caused by inter-clock skew is likely to make timing closure difficult during implementation. Investigate any inter-clock skew greater than 1.0 ns to ensure proper constraints or design topology.
The DRC reports that a large hold violation caused by inter-clock skew is likely to make timing closure difficult during implementation. Investigate any inter-clock skew greater than 1.0 ns to ensure proper constraints or design topology.