Description - Description - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2025-12-10
Version
2025.2 English

Do not apply a set_false_path, set_clock_group -asynchronous, or set_max_delay -datapath_only constraint to a synchronous clock domain crossing. Such constraints prevent the paths from being properly timed, resulting in inaccurate sign-off timing and potential hardware failure.