A primary clock must be defined at the source of the clock tree. For example, this would be the input port of the design. When a primary clock is defined in the middle of a logic path, timing analysis becomes inaccurate because it ignores the insertion delay before the primary clock source point. This prevents correct skew computation and can cause failures in hardware.
Creating a primary clock on an internal driver pin is discouraged. This practice can cause inaccurate timing analysis results and improper clock skew reporting.