Description - Description - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2025-12-10
Version
2025.2 English

The DRC warning occurs when a set_max_delay -datapath_only constraint is overridden by a set_clock_groups or set_false_path constraint between clocks. If a point-to-point set_false_path constraint overrides a set_max_delay -datapath_only constraint, the DRC is not reported.