Two categories of clocks are identified by the wizard, as shown in the following figure:
- The primary clocks needed for computing the timing slack for setup, hold, recovery, and removal checks appear in the Recommended Constraints table.
- The clocks only needed for performing pulse width checks
(min_period, max_period, max_skew, min_low_pulse_width, and min_high_pulse_width) appear in the Constraints for Pulse Width Check Only table. By default, these clocks are unchecked because they are only used for reporting purposes and do not influence the implementation tools quality of result.
The wizard automatically identifies the proper clock source point for the constraint. In most cases, the clock source point is an input clock port, and in some special cases, it is the output of a primitive that does not have a timing arc. For example, in 7 series devices, the wizard identifies missing primary clocks on the output of GT_CHANNEL primitives. For AMD UltraScale™ devices, the Vivado Design Suite is able to auto-derive the GT_CHANNEL output clocks based on the incoming clock characteristics and the GT_CHANNEL configuration and connectivity. Consequently, the wizard recommends primary clocks located upstream from the GT_CHANNEL cells on the design boundary.