The Timing Constraints wizard recommends the creation of a generated clock on the output of a sequential cell when it drives the clock pins of other sequential cells either directly or through some interconnect logic. Unlike PLL or MMCM, user logic cannot multiply the frequency of the master clock, so the wizard only offers the option to specify a division coefficient, as shown in the following figure:
When several master clocks reach the generated clock source point, the wizard creates all the corresponding generated clocks, using unique names and clear reference to individual master clocks. The previous figure illustrates the scenario where two clocks (clk3 and clk4) reach the sequential cell FDIV_reg. Consequently, two generated clock constraints (FDIV and FDIV_1) are recommended.