The MicroBlaze V soft core processor is highly configurable, allowing you to select a specific set of features required by your design.
The fixed feature set of the processor implements the RISC-V RV32I Base Integer Instruction Set and the machine-level ISA.
- 32 general purpose registers
- Extensible 32-bit program counter
- Single-issue pipeline
- Arithmetic logic unit (ALU)
- Barrel-shifter
- "Zicsr" control and status register (CSR) instructions
- "Zifencei" instruction-fetch fence
In addition to these fixed features, the MicroBlaze V processor is parameterized to allow selective enabling of additional functionality.
The following table provides an overview of the configurable features.
| Feature | Version |
|---|---|
| v1.0 | |
| RV64I Base Integer Instruction Set | Option |
| Processor pipeline depth | 3, 4, 5, 8 |
| "M" Standard Extension for Integer Multiplier and Divider | Option |
| "A" Standard Extension for Atomic Instructions | Option |
| "C" Standard Extension for Compressed Instructions | Option |
| "F" Standard Extension for Single-Precision Floating-Point | Option |
| "D" Standard Extension for Double Precision Floating Point | Option |
| "Zba", "Zbb", "Zbc", "Zbs" Bit-Manipulation ISA Extensions | Option |
| User-mode | Option |
| Physical Memory Protection | Option |
| "Smepmp" PMP Enhancements 1 | Option |
| Supervisor Level ISA 1 | Option |
| Page-Based Virtual Memory System 1 | Option |
| "Sstc" Extension for Supervisor-mode Timer Interrupts 1 | Option |
| "Smdbltrp" Double Trap Extension 1 | Option |
|
"Smrnmi" Extension for Resumable Non-Maskable Interrupts 1 |
Option |
| External debug support | Option |
| Parallel debug module interface | Option |
| Secure debug | Option |
| Branch target cache (BTC) | Option |
| Local memory bus (LMB) data side interface | Option |
| Local memory bus (LMB) instruction side interface | Option |
| Instruction and data caches with "Zicbom" Cache Block Management | Option |
| Cache line word length | 4, 8, 16 |
| LUT cache memory | Option |
| Use write-back caching policy for D-Cache | Option |
| Streams for I-Cache | Option |
| Victim handling for I-Cache | 0, 2, 4, 8 |
| Victim handling for D-Cache | 0, 2, 4, 8 |
| Force distributed RAM for cache tags | Option |
| Configurable cache data widths | Option |
| AXI4 (M_AXI_DP) data side interface | Option |
| AXI4 (M_AXI_IP) instruction side interface | Option |
| AXI4 (M_AXI_DC) protocol for D-Cache | Option |
| AXI4 (M_AXI_IC) protocol for I-Cache | Option |
| ACE (M_ACE_DC) protocol for D-Cache 1 | Option |
| ACE (M_ACE_IC) protocol for I-Cache 1 | Option |
| AXI4 non-secure mode | Option |
| Lockstep support | Option |
| Configurable use of FPGA primitives | Option |
| Relocatable base vectors | Option |
| Pipeline pause functionality | Option |
| Extended data addressing | Option |
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