The main objective of this step is to reduce risk and identify gaps in assumptions made earlier. With the strawman proposal planned, it is important to verify that the proposal will solve the problem.
For algorithms mapped to AI Engine, you can inspect the Vitis Libraries to see if an existing library block element matches your needs. If so, run quick simulations to understand throughput and latency performance of those library blocks.
Otherwise, it is useful to develop and investigate candidate vectorization options and consider how to use the SIMD processor to improve throughput. This might involve coding up kernels in isolation to identify the number of cycles required to loop through some data.
Algorithm Vectorization for AI Engine:
- Optimize data flow for efficient lane vectorization
- Early AI Engine API or intrinsic selection for key kernels
- Analysis of vector register requirements and utilization
- Visualize an plan lane assignments using Excel spreadsheets
Rapid Prototyping of AI Engine subsystems:
- Resource estimation including tile count, buffer usage, PLIO resources, stream array traffic, etc.
- Assess latency feasibility with early data flow simulations
- Assess throughput feasibility via prototype kernel coding, Initiation Interval (II) loop analysis, etc.
Similarly, for algorithms mapped to PL, if the algorithm was implemented on an earlier device or technology node, this process involves re-synthesizing the code on newer technology to get early estimates on PL resources needed (BRAM, LUTs, DSPs, FF, etc.) and assess Fmax feasibility. Alternatively, newer functionality can be rapidly prototyped using Vitis HLS.
Functionality that is mapped to the processor can also be implemented and profiled to understand performance.
Early Power Analysis can be performed using the Power Design Manager (PDM) for AI Engine, PL, embedded blocks, interfaces, etc. For more information, see the Power Design Manager User Guide (UG1556).
For designs using packet switching where interface bandwidth between the blocks can change depending on what is occurring in the system, traffic generator analysis needs to be performed. Here, the compute aspect of the system can be abstracted, and you can generate random source packets and inspect any possible bandwidth bottlenecks. For more information, see this link in the AI Engine Tools and Flows User Guide (UG1076).